Essenceia/CRC_generator
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. Written by Evgeni Stavinov.
0Active
On the radar — signal detected
Stars
4
Forks
0
Contributors
0
Language
C++
Score updated Jun 26, 2026
// SUBSCRIBE
The repos that moved this week, why they matter, and what to watch next. One email. No noise.